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ISL22313
Single Digitally Controlled Potentiometer (XDCPTM)
Data Sheet July 17, 2007 FN6421.0
Low Noise, Low Power, I2C(R) Bus, 256 Taps
The ISL22313 integrates a single digitally controlled potentiometer (DCP), control logic and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR control the position of the wiper. At power up the device recalls the contents of the DCP's IVR to the WR. The ISL22313 also has 14 general purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. The ISL22313 features a dual supply, that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* 256 resistor taps * I2C serial interface - Two address pins, up to four devices per bus * Non-volatile EEPROM storage of wiper position * 14 General Purpose non-volatile registers * High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T+55C * Wiper resistance: 70 typical @ 1mA * Standby current <2.5A max * Shutdown current <2.5A max * Dual power supply - VCC = 2.25V to 5.5V - V- = -2.25V to -5.5V * DCP terminal voltage from V- to VCC * 10k, 50k or 100k total resistance * Extended industrial temperature range: -40 to +125C * 10 Lead MSOP * Pb-free plus anneal product (RoHS compliant)
Pinout
ISL22313 (10 LD MSOP) TOP VIEW
SCL SDA A1 A0 V1 2 3 4 5 O 10 9 8 7 6 VCC RH RW RL GND
Ordering Information
PART NUMBER (Notes 1, 2) ISL22313TFU10Z ISL22313UFU10Z ISL22313WFU10Z NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "-TK" suffix for 1,000 Tape and Reel option PART MARKING 313TZ 313UZ 313WZ RESISTANCE OPTION (k) 100 50 10 TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-Free) 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP PKG. DWG. # M10.118 M10.118 M10.118
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL22313 Block Diagram
VCC V-
SCL SDA A1 A0 I2C INTERFACE
POWER UP INTERFACE, CONTROL AND STATUS LOGIC
RH
WR VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY
NON-VOLATILE REGISTERS RL RW GND
Pin Descriptions
MSOP PIN 1 2 3 4 5 6 7 8 9 10 SYMBOL SCL SDA A1 A0 VGND RL RW RH VCC Open drain I2C interface clock input Open drain Serial data I/O for the I2C interface Device address input for the I2C interface Device address input for the I2C interface Negative supply pin Device ground pin "Low" terminal of DCP "Wiper" terminal of DCP "High" terminal of DCP Power supply pin DESCRIPTION
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Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V Voltage at any DCP Pin with respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +125C ESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature (Plastic Package). . . . . . . . +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Full Industrial) . . . . . . . . . . . .-40C to +125C Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.25V to -5.5V Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
Over recommended operating conditions unless otherwise stated. Limits are established by characterization. MIN TYP MAX (Note 18) (Note 4) (Note 18) 10 50 100 -20 W option U, T option 150 50 V70 10/10/25 0.1 1 VCC 250 +20
SYMBOL RTOTAL
PARAMETER RH to RL resistance W option U option T option RH to RL resistance tolerance End-to-End Temperature Coefficient
TEST CONDITIONS
UNIT k k k % ppm/C ppm/C V pF A
VRH, VRL RW CH/CL/CW (Note 16) ILkgDCP
DCP terminal voltage Wiper resistance Potentiometer capacitance Leakage on DCP pins
VRH and VRL to GND RH - floating, VRL = V-, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL See Macro Model below. Voltage at pin from GND to VCC
VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; measured at RW, unloaded) INL (Note 9) Integral non-linearity W option U, T option DNL (Note 8) Differential non-linearity W option U, T option ZSerror (Note 6) FSerror (Note 7) Zero-scale error W option U, T option Full-scale error W option U, T option DCP register set to 80 hex -1.5 -1.0 -1.0 -0.5 0 0 -5 -2 0.5 0.2 0.4 0.15 1 0.5 -1 -1 4 1.5 1.0 1.0 0.5 5 2 0 0 LSB (Note 5) LSB (Note 5) ppm/C LSB (Note 5) LSB (Note 5)
TCV Ratiometric temperature coefficient (Notes 10, 16)
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Analog Specifications
Over recommended operating conditions unless otherwise stated. Limits are established by characterization. (Continued) TEST CONDITIONS Wiper at midpoint (80hex) W option (10k) Wiper at midpoint (80hex) U option (50k) Wiper at midpoint (80hex) T option (100k) MIN TYP MAX (Note 18) (Note 4) (Note 18) 1000 250 120 UNIT kHz kHz kHz
SYMBOL fcutoff (Note 16)
PARAMETER -3dB cut off frequency
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 14) Integral non-linearity W option U, T option RDNL (Note 13) Differential non-linearity W option U, T option Roffset (Note 12) Offset W option U, T option TCR Resistance temperature coefficient (Notes 15, 16) DCP register set between 32 hex and FF hex -3 -1 -1.5 -0.5 0 0 1.5 0.3 0.4 0.15 1 0.5 50 3 1 1.5 0.5 5 2 MI (Note 11) MI (Note 11) MI (Note 11) MI (Note 11) MI (Note 11) MI (Note 11) ppm/C
Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by
characterization. SYMBOL ICC1 PARAMETER VCC Supply Current (volatile write/read) TEST CONDITIONS VCC = +5.5V, V- = -5.5V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) VCC = +2.25V, V- = -2.25V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) IV-1 V- Supply Current (volatile write/read) V- = -5.5V, VCC = +5.5V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) V- = -2.25V, VCC = +2.25V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) ICC2 VCC Supply Current (non-volatile write/read) VCC = +5.5V, V- = -5.5V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) VCC = +2.25V, V- = -2.25V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) IV-2 V- Supply Current (non-volatile write/read) V- Supply Current (non-volatile write/read) V- = -5.5V, VCC = +5.5V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) V- = -2.25V, VCC = +2.25V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) -2 -1 MIN (Note 18) TYP (Note 4) 0.07 MAX (Note 18) 0.15 UNIT mA
0.02
0.05
mA
-0.18
mA
-0.4
-0.06
mA
1
2
mA
0.3
0.7
mA
-1.2
mA
-0.7
-0.4
mA
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Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by
characterization. (Continued) SYMBOL ISB PARAMETER VCC Current (standby) TEST CONDITIONS VCC = +5.5V, V- = -5.5V @ +85C, I2C interface in standby state VCC = +5.5V, V- = -5.5V @ +125C, I2C interface in standby state VCC = +2.25V, V- = -2.25V @ +85C, I2C interface in standby state VCC = +2.25V, V- = -2.25V @ +125C, I2C interface in standby state IV-SB V- Current (standby) V- = -5.5V, VCC = +5.5V @ +85C, I2C interface in standby state V- = -5.5V, VCC = +5.5V @ +125C, I2C interface in standby state V- = -2.25V, VCC = +2.25V @ +85C, I2C interface in standby state V- = -2.25V, VCC = +2.25V @ +125C, I2C interface in standby state ISD VCC Current (shutdown) VCC = +5.5V, V- = -5.5V @ +85C, I2C interface in standby state VCC = +5.5V, V- = -5.5V @ +125C, I2C interface in standby state VCC = +2.25V, V- = -2.25V @ +85C, I2C interface in standby state VCC = +2.25V, V- = -2.25V @ +125C, I2C interface in standby state IV-SB V- Current (standby) V- = -5.5V, VCC = +5.5V @ +85C, I2C interface in standby state V- = -5.5V, VCC = +5.5V @ +125C, I2C interface in standby state V- = -2.25V, VCC = +2.25V @ +85C, I2C interface in standby state V- = -2.25V, VCC = +2.25V @ +125C, I2C interface in standby state ILkgDig tDCP (Note 16) tShdnRec (Note 16) Vpor Leakage current, at pins A0, A1, SDA, Voltage at pin from GND to VCC and SCL DCP wiper response time SCL falling edge of last bit of DCP data byte to wiper new position -2.5 -4 -1.5 -3 -1 1.5 1.5 1.9 0.2 VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state 5 2.1 -2.5 -4 -1.5 -3 1 0.1 0.5 -0.7 -3 -0.3 -1 0.2 1 0.1 0.5 -0.7 -3 -0.3 -1 1 1.5 2.5 1 2 2.5 1 2 A A A A A A A A A A A A A A A A s s V V/ms ms MIN (Note 18) TYP (Note 4) 0.2 MAX (Note 18) 1.5 UNIT A
DCP recall time from shutdown mode SCL falling edge of last bit of ACR data byte to wiper stored position and RH connection Power-on recall voltage Minimum VCC at which memory recall occurs
VCC Ramp VCC ramp rate tD Power-up delay
EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 17) Non-volatile Write cycle time Temperature T +55C 1,000,000 50 12 20 Cycles Years ms
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Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by
characterization. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 18) TYP (Note 4) MAX (Note 18) UNIT
SERIAL INTERFACE SPECS VIL VIH Hysteresis (Note 16) VOL (Note 16) Cpin (Note 16) fSCL tsp tAA (Note 16) tBUF (Note 16) tLOW tHIGH tSU:STA tHD:STA tSU:DAT A1, A0, SDA, and SCL input buffer LOW voltage A1, A0, SDA, and SCL input buffer HIGH voltage SDA and SCL input buffer hysteresis SDA output buffer LOW voltage, sinking 4mA A1, A0, SDA, and SCL pin capacitance SCL frequency Pulse width suppression time at SDA and SCL inputs SCL falling edge to SDA output data valid Time the bus must be free before the start of a new transmission Clock LOW time Clock HIGH time START condition setup time START condition hold time Input data setup time Any pulse narrower than the max spec is suppressed SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition Measured at the 30% of VCC crossing Measured at the 70% of VCC crossing SCL rising edge to SDA falling edge; both crossing 70% of VCC From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC From SDA rising edge to SCL falling edge; both crossing 70% of VCC From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window From 30% to 70% of VCC From 70% to 30% of VCC Total on-chip and off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2k~2.5k For Cb = 40pF, max is about 15k~20k 1300 -0.3 0.7*VCC 0.05*VCC 0 0.4 10 400 50 900 0.3*VCC VCC + 0. 3 V V V V pF kHz ns ns ns
1300 600 600 600 100
ns ns ns ns ns
tHD:DAT
Input data hold time
0
ns
tSU:STO tHD:STO tDH (Note 16) tR (Note 16) tF (Note 16) Cb (Note 16) Rpu (Note 16)
STOP condition setup time STOP condition hold time for read, or volatile only write Output data hold time
600 1300 0
ns ns ns
SDA and SCL rise time SDA and SCL fall time Capacitive loading of SDA or SCL SDA and SCL bus pull-up resistor off-chip
20 + 0.1 * Cb 20 + 0.1 * Cb 10 1
250 250 400
ns ns pF k
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Operating Specifications Over the recommended operating conditions unless otherwise specified. Limits are established by
characterization. (Continued) SYMBOL tSU:A tHD:A NOTES: 4. Typical values are for TA = +25C and 3.3V supply voltage. 5. LSB: [V(RW)255 - V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 6. ZS error = V(RW)0/LSB. 7. FS error = [V(RW)255 - VCC]/LSB. 8. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 9. INL = [V(RW)i - i * LSB - V(RW)0]/LSB for i = 1 to 255 Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 10. TC = --------------------------------------------------------------------------------------------- x ---------------- for i = 16 to 255 decimal, T = -40C to +125C. Max( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 +165C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 11. MI = |RW255 - RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 12. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW255/MI, when measuring between RW and RH. 13. RDNL = (RWi - RWi-1)/MI -1, for i = 16 to 255. 14. RINL = [RWi - (MI * i) - RW0]/MI, for i = 16 to 255. for i = 16 to 255, T = -40C to +125C. Max( ) is the maximum value of the resistance and Min ( ) is [ Max ( Ri ) - Min ( Ri ) ] 10 TC R = --------------------------------------------------------------- x ---------------- the minimum value of the resistance over the temperature range. 165C [ Max ( Ri ) + Min ( Ri ) ] 2 + 16. Limits should be considered typical and are not production tested. 17. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile write cycle. 18. Parts are 100% tested at +25C. Over temperature limits established by characterization and are not production tested. 15.
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PARAMETER A1 and A0 setup time A1 and A0 hold time
TEST CONDITIONS Before START condition After STOP condition
MIN (Note 18) 600 600
TYP (Note 4)
MAX (Note 18)
UNIT ns ns
DCP Macro Model
RTOTAL RH CH CW CL 10pF RL
10pF RW
25pF
SDA vs SCL Timing
tF tHIGH tLOW tR tsp
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
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A0 and A1 Pin Timing
START SCL CLK 1 STOP
SDA tSU:A A0, A1 tHD:A
Typical Performance Curves
80 T = +125C 70 WIPER RESISTANCE () STANDBY CURRENT (A) 60 T = +25C 50 40 30 20 10 0 0 50 100 150 200 250 TAP POSITION (DECIMAL) T = -40C 1.5 1.0 0.5 0 -0.5 IV-1.0 -1.5 -2.0 -40 ICC 2.0
0
40 TEMPERATURE (C)
80
120
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W)
FIGURE 2. STANDBY ICC AND IV- vs TEMPERATURE
0.50 T = +25C VCC = 2.25V 0.25 DNL (LSB)
0.50 VCC = 5.5V 0.25 T = +25C
INL (LSB) VCC = 5.5V
0
0
-0.25
-0.25
VCC = 2.25V -0.50 200 250 0 50 100 150 200 250
-0.50 0 50 100 150 TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
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2.0 10k 1.6 FS ERROR (LSB) -1
(Continued)
0
VCC = 2.25V 50k VCC = 5.5V
ZS ERROR (LSB)
1.2
-2
0.8 VCC = 2.25V 0.4
50k VCC = 5.5V
-3
10k
-4
0 -40
0
40 TEMPERATURE (C)
80
120
-5 -40
0
40 TEMPERATURE (C)
80
120
FIGURE 5. ZS ERROR vs TEMPERATURE
FIGURE 6. FS ERROR vs TEMPERATURE
0.5 T = +25C 0.25 RDNL (MI) VCC = 5.5V
2.0 T = +25C 1.5 VCC = 2.25V
1.0 0 RINL (MI) VCC = 2.25V -0.50 0 50 100 150 200 250 TAP POSITION (DECIMAL) -0.5 0
0.5
-0.25 0 VCC = 5.5V 50 100 150 200 250
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
200
1.60 10k 1.20 RTOTAL CHANGE (%)
160 10k TCv (ppm/C)
0.80
120
5.5V
0.40
80
0.00 2.25V -0.40 -40 0 40 TEMPERATURE (C) 80 50k
40
50k
0 120
16
66
116
166
216
266
TAP POSITION (DECIMAL)
FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
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ISL22313 Typical Performance Curves
500
(Continued)
INPUT
400 10k
OUTPUT
TCr (ppm/C)
300
200 50k 100 WIPER AT MID POINT (POSITION 80h) RTOTAL = 10k 16 66 116 166 216 TAP POSITION (DECIMAL)
0
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (1MHz)
CS SCL
WIPER UNLOADED, WIPER MOVEMENT FROM 0h to FFh
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
FIGURE 14. LARGE SIGNAL SETTLING TIME
Pin Description
Potentiometers Pins
RH and RL The high (RH) and low (RL) terminals of the ISL22313 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 255 decimal, the wiper will be closest to RH, and with the WR set to 0, the wiper is closest to RL. RW RW is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register.
Bus Interface Pins
Serial Data Input/Output (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. Serial Clock (SCL) This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor, since it is an open drain input.
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Device Address (A1, A0) The address inputs are used to set the least significant 2 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL22313. A maximum of four ISL22313 devices may occupy the I2C serial bus (see Table 3).
Memory Description
The ISL22313 contains one non-volatile 8-bit Initial Value Register (IVR), fourteen General Purpose non-volatile 8-bit registers and two volatile 8-bit registers: Wiper Register (WR) and Access Control Register (ACR). Memory map of ISL22313 is in Table 1. The non-volatile register (IVR) at address 0, contains initial wiper position and volatile register (WR) contains current wiper position.
TABLE 1. MEMORY MAP ADDRESS (hex) 10 F E D C B A 9 8 7 6 5 4 3 2 1 0 General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose IVR NON-VOLATILE N/A Reserved N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A WR VOLATILE ACR
Principles of Operation
The ISL22313 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the contents of the IVR are recalled and loaded into the WR to set the wiper to the initial value.
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR[7:0]= 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR register of a DCP contains all ones (WR[7:0]= FFh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL22313 is being powered up, the WR is reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reloaded with the value stored in a non-volatile Initial Value Register (IVR). The WR and IVR can be read or written to directly using the I2C serial interface as described in the following sections.
The non-volatile IVR and volatile WR registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described below in Table 2. The VOL bit (ACR[7]) determines whether the access to wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # NAME 7 VOL 6 SHDN 5 WIP
4 0
3 0
2 0
1 0
0 0
If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WR is accessible. Note: Value is written to IVR register also is written to the WR. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. When this bit is 0, i.e. DCP is forced to end-to-end open circuit and RW is shorted to RL as shown on Figure 15. Default value of the SHDN bit is 1.
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ISL22313
RH
RW
All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22313 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 16). A START condition is ignored during the powerup of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 16). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 17). The ISL22313 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22313 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 10100 as the five MSBs, and the following two bits matching the logic values present at pins A1 and A0. The LSB is the Read/Write bit. Its value is "1" for a Read operation and "0" for a Write operation (see Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY
RL
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
The WIP bit (ACR[5]) is a read-only bit. It indicates that nonvolatile write operation is in progress. It is impossible to write to the WR or ACR while WIP bit is 1.
I2C Serial Interface
The ISL22313 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL22313 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 16). On power-up of the ISL22313, the SDA pin is in the input mode.
1 (MSB)
0
1
0
0
A1
A0
R/W (LSB)
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
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ISL22313
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE SLAVE
1 0 1 0 0 A1 A0 0 A C K
0000 A C K A C K
FIGURE 18. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W = 0
ADDRESS BYTE
S T A IDENTIFICATION R BYTE WITH T R/W = 1
A C K
A C K
S AT CO KP
SIGNAL AT SDA
1 0 1 0 0 A1 A0 0 A C K
0000 A C K
1 0 1 0 0 A1 A0 1 A C K
SIGNALS FROM THE SLAVE
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 19. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22313 responds with an ACK. At this time, the device enters its standby state (see Figure 18). The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next non-volatile write. Thus, non-volatile registers must be written individually.
Read Operation
A Read operation consist of a three byte instruction followed by one or more Data Bytes (see Figure 19). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL22313 responds with an ACK. Then the ISL22313 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and
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ISL22313
increments by one during transmission of each Data Byte. After reaching the memory location 0Fh, the pointer "rolls over" to 00h, and the device continues to output data for each ACK received.The master terminates the read operation issuing a NACK (ACK ) and a STOP condition following the last bit of the last Data Byte (see Figure 19).
Applications Information
When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients (or overshoot/undershoot) resulting from the sudden transition from a very low impedance "make" to a much higher impedance "break within an extremely short period of time (<50ns). Two such code transitions are EFh to F0h, and 0Fh to 10h. Note that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus this may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery.
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FN6421.0 July 17, 2007
ISL22313 Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -CL L1 4X R1 R 0.20 (0.008) ABC E
INCHES SYMBOL A A1 A2 b c D
4X
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o
MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028
INDEX AREA
E1 e E L L1 N R R1
-B-
A
A2
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
SIDE VIEW
15o 6o
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN6421.0 July 17, 2007

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